1. Field of Disclosure
The present disclosure is related to the field of time to digital converters. For example, the present disclosure relates to systems, circuits, and methods for a sigma-delta based time to digital converter.
2. Related Art
Phase-locked loops (PLLs) may be used to generate an output signal based on an input reference signal. A conventional PLL comprises a phase detector to compare the phase of an input signal with the phase of a feedback signal of the output of an oscillator and adjusts the frequency of the oscillator until the phases of the reference signal and feedback signal match. PLLs may be implemented in the digital domain. However, conventional digital PLLs are typically associated with design limitations such as low accuracy, large area, and high power consumption.
Accordingly, it is highly desirable to develop systems, circuits and methods for a digital PLL. For example, it is highly desirable to implement components of a PLL that may provide a high accuracy for time-to-digital conversion.
The disclosure will now be described with reference to the accompanying drawings. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the reference number.